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74LVT322373 * 74LVTH322373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 25 Series Resistors in the Outputs
May 2002 Revised May 2002
74LVT322373 * 74LVTH322373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 25 Series Resistors in the Outputs
General Description
The LVT322373 and LVTH322373 contain thirty-two noninverting latches with 3-STATE outputs and are intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LVTH322373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These latches are designed for low voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT322373 and LVTH322373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH322373), also available without bushold feature (74LVT322373) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs include equivalent series resistance of 25 to make external termination resistors unnecessary and reduce overshoot and undershoot s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LVT322373G (Note 1) (Note 2) 74LVTH322373G (Note 1) (Note 2) Package Number BGA96A (Preliminary) BGA96A Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering Code "G" indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
(c) 2002 Fairchild Semiconductor Corporation
DS500742
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74LVT322373 * 74LVTH322373
Connection Diagram
Pin Descriptions
Pin Names OEn LEn I0-I31 O0-O31 Description Output Enable Input (Active LOW) Latch Enable Input Inputs 3-STATE Outputs
FBGA Pin Assignments
1 A B C D E F G (Top Thru View) H J K L M N P R T O1 O3 O5 O7 O9 O11 O13 O14 O17 O19 O21 O23 O25 O27 O29 O30 2 O0 O2 O4 O6 O8 O10 O12 O15 O16 O18 O20 O22 O24 O26 O28 O31 3 OE1 GND VCC1 GND GND VCC1 GND OE2 OE3 GND VCC2 GND GND VCC2 GND OE4 4 LE1 GND VCC1 GND GND VCC1 GND LE2 LE3 GND VCC2 GND GND VCC2 GND LE4 5 I0 I2 I4 I6 I8 I10 I12 I15 I16 I18 I20 I22 I24 I26 I28 I31 6 I1 I3 I5 I7 I9 I11 I13 I14 I17 I19 I21 I23 I25 I27 I29 I30
Truth Table
Inputs LE1 X H H L OE1 H L L L Inputs LE3 X H H L
H = HIGH Voltage Level
Outputs I0-I7 X L H X O0-O7 Z L H O0 Outputs I16-I23 X L H X O16-O23 Z L H O0
X = Immaterial
Inputs LE2 X H H L OE2 H L L L Inputs LE4 X H H L
Z = HIGH Impedance
Outputs I8-I15 X L H X O8-O15 Z L H O0 Outputs I24-I31 X L H X O24-O31 Z L H O0
OE3 H L L L
OE4 H L L L
L = LOW Voltage Level
Oo = Previous Oo prior to HIGH-to-LOW transition of LE
Functional Description
The LVT322373 and LVTH322373 contain thirty-two D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 32-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. www.fairchildsemi.com 2
74LVT322373 * 74LVTH322373
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
VCC1 is associated with Bytes 1 and 2. VCC2 is associated with Bytes 3 and 4.
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT322373 * 74LVTH322373
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
64 128 -65 to +150
C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V to 2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
-12
12
-40
0
85 10
C
ns/V
t/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH VOL II(HOLD) II(OD) II Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH+ ICCH ICCL ICCZ Power Off Leakage Current Power up/down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current (VCC1 or VCC2) (VCC1 or VCC2) (VCC1 or VCC2) VCC (V) 2.7 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 3.0 2.7 3.0 3.0 3.0 3.6 3.6 3.6 0 0 - 1.5V 3.6 3.6 3.6 3.6 3.6 3.6 75 -75 500 -500 10 1 -5 1 100 100 -5 5 10 0.19 5 0.19 A A A A A mA mA mA A VCC - 0.2 2.0 0.2 0.8 2.0 0.8 T A = -40C to +85C Min Max -1.2 Units V V V V V A A Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -12 mA IOL = 100 A IOL = 12 mA VI = 0.8V VI = 2.0V (Note 5) (Note 6) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.5V VO = 3.0V VCC < VO 5.5V Outputs HIGH Outputs LOW Outputs Disabled
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74LVT322373 * 74LVTH322373
DC Electrical Characteristics
Symbol ICCZ+ ICC Parameter Power Supply Current Increase in Power Supply Current (Note 7)
(Continued)
VCC (V) T A = -40C to +85C Min Max 0.19 0.2 mA mA VCC VO 5.5V, Outputs Disabled One Input at V CC - 0.6V Other Inputs at VCC or GND
Units
Conditions
(VCC1 or VCC2) (VCC1 or VCC2)
3.6 3.6
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 8)
TA = 25C Min Typ 0.8 -0.8 Max Conditions Units V V CL = 50 pF, RL = 500 (Note 9) (Note 9)
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = -40C to +85C, CL= 50pF, RL= 500 Symbol Parameter VCC = 3.3V 0.3V Min tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Setup Time, Dn to LE Hold Time, Dn to LE LE Pulse Width Output to Output Skew (Note 10) Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.3 1.4 1.7 1.4 1.6 1.0 1.6 1.8 1.0 1.0 3.0 1.0 1.0 Max 4.8 4.8 5.0 5.1 5.0 5.4 5.1 5.4 Min 1.3 1.4 1.7 1.4 1.6 1.0 1.6 1.8 0.8 1.1 3.0 1.0 1.0 VCC = 2.7V Max 5.3 5.1 5.1 5.8 6.0 6.6 5.0 5.7 ns ns ns ns ns ns ns ns Units
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 11)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VCC = Open, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74LVT322373 * 74LVTH322373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 25 Series Resistors in the Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A Preliminary
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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